1. Field
The present invention relates neuromorphic systems, and in particular, to a Multiple Input Multiple Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system for inter-device communication.
2. Background
Neuromorphic systems are electronic systems that may be configured to operate and model the function of the biological brain. These systems may include processing elements or circuits that mimic biological neurons and synapses. As the number of neurons and synapses increases, multiple neuromorphic devices are needed due to the constraints on the maximum device die size available using current processes.
Address event representation (AER) is a protocol that may be used in inter-device communication in neuromorphic systems. The communication is modeled by looking at the action potentials or spikes representing data. AER employs time-multiplexing for encoding spiking data from several groups of neurons into a single communication bus. Transceivers encode and decode spikes over a small set of high-speed wires by encoding each axon with a unique binary representation called an address-event. Neurons are grouped together to share a common encoder and a decoder to reduce device space requirements.
The address packets generated during spike events are transferred and delivered by routers and have been used in neuromorphic systems. The packets are delivered on a neuron-by-neuron basis in the network. During each packet delivery, the packets are sequentially decoded, searched through a look-up table, delivered to the router, and eventually forwarded to the appropriate target neuron. This type of packet delivery is also known as point-to-point connectivity, and may result in several communication issues. For example, data rate and capacity may be limited. Additionally, deadlock and livelock may occur, which may postpone packet delivery forever in the network without reaching the destination causing timing errors in spikes and affecting the performance and accuracy in devices with spike-timing dependent plasticity (STDP) or other timing dependent rules. Further, if the system is subject to traffic jams or constraints at a certain node, a system failure may occur. Another problem that may occur is that the look-up table in each node may consume substantial memory for the system.
Several examples of communication systems that have experienced the above described communication issues include K. A. Boahen, “Point-to-point Connectivity between Neuromorphic Chips Using Address-Events,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 47, No. 5, 416-434, May 2000; A. Merolla, J. V. Arthur, B. E. Shi, and K. A. Boahen, “Expandable Networks for Neuromorphic Chips,” IEEE Transaction on Circuits and Systems I: Regular Paper, Vol. 54, No. 2, 301-311, February, 2007; C. Bartolozz and G. Indiveri, “Selective Attention in Multi-chip Address-Event Systems,” Sensors 2009, 9, 5076-5098; J. Aweya, “On the Design of IP routers Part 1: Router Architectures”, Journal of Systems Architecture, 46 (2000) 483-511; S. Felperin, P. Raghavan, and E. Upfal, “A Theory of Wormhole Routing in Parallel Computers,” IEEE Transaction on Computers, Vol. 45, No. 6, 704-713, June 1996; S. Badrouchi, A. Zitoumi, K. Torki, and R. Tourki, “Asynchronous NoC Router Design,” Journal of Computer Science 1(3): 429-436, 2005; L. A. Plana, S. B. Furber, S. Temple, M. Khan, Y. Shi, J. Wu, and S. Yang, “A GALS Infrastructure for Massively Parallel Multi-processor,” IEEE Design and Test of Computers, 24(5): 454-463, September-October, 2007; R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodriguez, L. Camuñas-Mesa, R. Berner, M. Rivas-Pérez, T. Delbrück, S. Liu, R. Douglas, P. Häfliger, G. Jiménez-Moreno, A. Civit Ballcels, T. Serrano-Gotarredona, A. J. Acosta-Jiménez, and B. Linares-Barranco, “CAVIAR: A 45 k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing-Learning-Actuating System for High-Speed Visual Object Recognition and Tracking,” IEEE Transactions on Neural Networks, Vol. 20, No. 9, 1417-1438, September 2009; J. Wu, “A Router for Massively-parallel Neural Simulation,” Ph.D thesis, University of Manchester; M. Vetterli, “A Theory of Multirate Filter Banks,” IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 35, no. 3, 356-372, 1987; P. P. Vaidyanathan, “Multirate Systems and Filter Banks”, Prentice-Hall, 1993; H. Scheuermann and H. Gockler, “A Comprehensive Survey of Digital Transmultiplexing Methods,” Proceeding of IEEE, Vol. 69, No. 11, 1419-1450, November, 1981.